Computer ScienceFoundation20 min read

Digital Systems and Logic Design

Gates, truth tables, and building arithmetic out of switches

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01

Two values, and the operations on them

Digital electronics works with exactly two values, written 1 and 0, or true and false, or high and low voltage. Boolean algebra is the mathematics of those two values, and a logic gate is the physical circuit that carries out one Boolean operation.

Everything a computer does is built from these. An adder is gates. A memory cell is gates. The whole processor is millions of them wired together, which is why this chapter sits underneath everything else in the subject.

GateSymbol in algebraOutput is 1 when…
NOTA′ or Āthe input is 0 — it simply inverts
ANDA · Bboth inputs are 1
ORA + Bat least one input is 1
NAND(A · B)′NOT both — the opposite of AND
NOR(A + B)′neither input is 1
XORA ⊕ Bthe inputs differ

Toggle the inputs and watch the output. XOR is the one worth studying — it outputs 1 only when the inputs disagree, which is exactly the behaviour a binary adder needs.

02

Truth tables

A truth table lists every possible combination of inputs and the output for each. Two inputs give 2² = 4 rows; three inputs give 8. Write the rows in a fixed order — 00, 01, 10, 11 — and none will be missed.

For a circuit made of several gates, add one column per intermediate signal. Fill the columns left to right, and the final column is the circuit's behaviour. This is how you prove two different circuits do the same job: build both tables and compare them row by row.

Worked example

Build the truth table for X = (A · B)′ + C.

  1. Three inputs, so there are 2³ = 8 rows.Count the rows before drawing the table; an incomplete table cannot score full marks.
  2. Add a column for A · B, which is 1 only in the rows where both A and B are 1.Work outward from the innermost bracket, exactly as in arithmetic.
  3. Add a column for (A · B)′, which is the previous column inverted.The NOT applies to the whole bracket, not to A alone.
  4. The output is that column OR C: 1 wherever either is 1.X is 0 only in the two rows where A and B are both 1 and C is 0.

X = 0 only when A = 1, B = 1 and C = 0; X = 1 in the other six rows.

03

Boolean algebra and simplification

Circuits cost money and power, so a design that uses four gates is worse than an equivalent one using two. Boolean algebra is how you get from the first to the second, and the laws below are the tools.

Most of them look like ordinary algebra. Two do not, and those two are where the marks are.

A + 0 = AA · 1 = AA + 1 = 1A · 0 = 0A + A = AA · A = A(idempotent)A + A′ = 1A · A′ = 0(complement)A + A·B = A(absorption)(A · B)′ = A′ + B′(A + B)′ = A′ · B′(De Morgan)De Morgan: break the bar and change the sign — it converts between AND and OR forms
Worked example

Simplify X = A·B + A·B′.

  1. Both terms share the factor A, so take it out: A·(B + B′).Factorising is the first move in almost every simplification.
  2. B + B′ = 1 by the complement law — B is either true or false, so one of the two must hold.This is the law that does the real work here.
  3. X = A · 1 = A.Two gates and an inverter reduced to a plain wire. Verify with a truth table: X matches A in all four rows ✓

X = A

The two that are not like ordinary algebra

A + A = A, not 2A — there is no 2 in Boolean algebra. And A + 1 = 1, not 2: once one input to an OR is true, the output is true whatever else happens. Students carry decimal habits into these and lose marks on the very first line of a simplification.

04

Building arithmetic from gates

The reason gates matter is that they can add. A half adder takes two bits and produces a sum and a carry: the sum is A ⊕ B and the carry is A · B. Check it against the binary rules — 1 + 1 gives sum 0, carry 1, which is exactly what XOR and AND produce.

A half adder cannot accept a carry coming in from the column to its right, so it is useless beyond the first column. A full adder takes three inputs — A, B and carry-in — and chaining eight of them together builds an 8-bit adder. That circuit is inside the ALU of every processor.

half adder:Sum = A ⊕ BCarry = A · Bfull adder:Sum = A ⊕ B ⊕ CinCout = A·B + Cin·(A ⊕ B)NAND and NOR are called universal gates because any circuit at all can be built from copies of just one of them

Before you leave this chapter

  1. AND needs both, OR needs at least one, NOT inverts, XOR needs them to differ.
  2. n inputs give 2ⁿ rows in the truth table — write them in a fixed order.
  3. A + A = A and A + 1 = 1. Boolean algebra has no 2.
  4. De Morgan: (A·B)′ = A′ + B′ and (A+B)′ = A′·B′.
  5. Half adder = XOR for sum, AND for carry. A full adder also takes a carry in.
05

From a problem in words to a circuit

The examinable skill that ties this chapter together is turning a description into a Boolean expression and then into a circuit. The method is mechanical once you see it.

Write a truth table with one row per input combination. For every row where the output is 1, write the product of the inputs — using the variable where it is 1 and its complement where it is 0. Then OR all those products together. The result is called the sum of products form, and it always works.

Worked example

An alarm sounds when the door is open (D = 1) AND either the system is armed (A = 1) or the panic button is pressed (P = 1). Write the expression and simplify.

  1. Translate directly: "door open AND (armed OR panic)" becomes X = D · (A + P).Read the sentence for the word "and" and the word "or"; the brackets follow the grouping in the English.
  2. Expanding gives X = D·A + D·P, the sum-of-products form.Both forms are correct. The bracketed one uses fewer gates; the expanded one is easier to read off a truth table.
  3. Gate count: the bracketed version needs one OR and one AND — two gates.The expanded version needs two ANDs and one OR — three gates for identical behaviour.
  4. So the factorised form is the better circuit.Fewer gates means lower cost, less power and less delay. That is why simplification is worth doing at all.

X = D · (A + P), using two gates rather than three

Reading the English carefully

The word "or" in a specification is almost always inclusive — armed or panic or both. If a question genuinely means one or the other but not both, it will say so, and that is XOR rather than OR. Underline the ands and ors in the question before writing a single symbol.

Practice questions

6 questions · 20 marks · full working on every one

Try each one on paper first, then open the working. The marks are shown where they are actually awarded, because that is where they are actually lost.

Short questions

3 · 6 marks

Two marks each, in the style of the short-question section of the paper. Answer in two or three lines.

SQ1[2 marks]
Draw the truth table for a two-input NAND gate.
Model answer

Inputs 00 → 1, 01 → 1, 10 → 1, 11 → 0. NAND is the inverse of AND, so it outputs 0 only when both inputs are 1.

Examiner tip. Say what it is the inverse of. That sentence secures the mark even if a row is written wrongly.

SQ2[2 marks]
State De Morgan's two laws.
Model answer

(A · B)′ = A′ + B′ and (A + B)′ = A′ · B′. Complementing a whole expression swaps AND for OR and complements each variable.

Examiner tip. Both laws are needed for two marks. The summary "break the bar and change the sign" is worth adding as it shows you know how to apply them.

SQ3[2 marks]
Why are NAND and NOR called universal gates?
Model answer

Because any logic function whatsoever can be built using copies of just one of them. NOT, AND, OR and every larger circuit can be constructed from NAND alone, or from NOR alone, which is why chip manufacturers can make a whole processor from one repeated gate design.

Examiner tip. The practical reason — one gate design to manufacture — is often the second mark.

Solved numericals

2 · 8 marks

Full working, one step per line, with the marks shown where they are awarded.

N1[4 marks]
Construct the truth table for X = A′ · B + A · B′ and state which single gate it is equivalent to.
Full working
  1. Four rows for two inputs, with columns for A′ and B′[1]
  2. A=0,B=0 → 0; A=0,B=1 → 1A′·B is 1 in the second row[1]
  3. A=1,B=0 → 1; A=1,B=1 → 0[1]
  4. Output is 1 exactly when the inputs differ, so this is an XOR gatethe identification is the point of the question[1]

The table matches XOR: output 1 when A and B differ.

Examiner tip. This expression IS the standard definition of XOR in terms of the basic gates, and it is worth memorising — it appears in half adder questions too.

N2[4 marks]
Simplify X = (A + B) · (A + B′) using Boolean laws, naming each law you use.
Full working
  1. Expand: A·A + A·B′ + B·A + B·B′distributive law[1]
  2. A·A = A (idempotent) and B·B′ = 0 (complement)[1]
  3. X = A + A·B′ + A·Bthe zero term disappears[1]
  4. By absorption A + A·anything = A, so X = Anaming the law is required by the question[1]

X = A

Examiner tip. Name the law at every step. The question says "naming each law", so an unnamed but correct simplification loses marks it did not need to.

Long questions

1 · 6 marks

Theory and numerical together, as they appear in the long-question section.

LQ1[6 marks]
A half adder adds two single bits.
  1. Write the truth table showing Sum and Carry for the four input combinations.
  2. State which gate produces the Sum and which produces the Carry.
  3. Explain why a half adder cannot be used for the second column of a multi-bit addition.
Mark scheme
  1. 0+0 → Sum 0, Carry 0; 0+1 → Sum 1, Carry 0[1]
  2. 1+0 → Sum 1, Carry 0; 1+1 → Sum 0, Carry 1the last row is the whole point — 1+1 in binary is 10[1]
  3. Sum is produced by an XOR gateoutput 1 when the inputs differ[1]
  4. Carry is produced by an AND gateoutput 1 only when both are 1[1]
  5. A half adder has only two inputs, so it has nowhere to accept the carry produced by the previous column[1]
  6. A full adder is needed instead, taking three inputs — A, B and carry-innaming the full adder is expected[1]

(b) XOR for Sum, AND for Carry (c) it has no carry-in input, so a full adder is required

Examiner tip. Check the half adder table against ordinary binary addition: 1 + 1 = 10, which is sum 0 carry 1. If your table disagrees with binary arithmetic, the table is wrong.